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HardWaves One Registers

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HardWaves One Application Registers

HardWaves One I/O can be fully programmed to process both digital or analog signals.

Back to Data_Registers.

Reg#
Name
Mode
Unit
Value
2 REG_PHY_CLASS RO [] 0
3 REG_PHY_TYPE RO [] 1
64 REG_APP_VERSION RO [] 0x1000
65 REG_STATUS_A RO [] BIT[0..3]→ In [0..3]
BIT[4..7]→ Out [0..3]
BIT[8..10]→ FREE
BIT[11]→ External Power Only (no battery)
BIT[12..14]→ BATT Level
BIT[15] → BATT Change
66 REG_STATUS_B RO [] BIT[0..2] → ADC0 Level
BIT[3] → ADC0 Change
BIT[4..6] → ADC1 Level
BIT[7] → ADC1 Change
BIT[8..10] → ADC2 Level
BIT[11] → ADC2 ChangeBIT[12..14] → ADC3 Level
BIT[15] → ADC3 Change
67 REG_SET_OUT0 RW [s] 0x0000 → OFF
0xFFFF → ON forever
n → ON for 'n' [s] (Read returns remaining time)
68 REG_SET_OUT1 RW [s] 0x0000 → OFF
0xFFFF → ON forever
n → ON for 'n' [s] (Read returns remaining time)
69 REG_SET_OUT2 RW [s] 0x0000 → OFF
0xFFFF → ON forever
n → ON for 'n' [s] (Read returns remaining time)
70 REG_SET_OUT3 RW [s] 0x0000 → OFF
0xFFFF → ON forever
n → ON for 'n' [s] (Read returns remaining time)
71 REG_ADC_BATT RO [mV]
72 REG_ADC_IN0 RO [mV]
73 REG_ADC_IN1 RO [mV]
74 REG_ADC_IN2 RO [mV]
75 REG_ADC_IN3 RO [mV]
76 REG_AUTOSEND_TIME RW [s]
77 REG_PORT_SETUP RW [] BIT[0..3] → Analog Input Mask
BIT[4..7] → IRQ Enable Mask
BIT[8..11] → REN (Resistor ENable)
BIT[12..15] → UP/DOWN (if REN bit is set)
78 REG_DIG_IN0_SETUP RW [] BIT BIT[0..7] → Time
BIT[8..15] → Count
Set 0xFFFF (65535) for up-counter mode
79 REG_DIG_IN1_SETUP RW [] BIT BIT[0..7] → Time
BIT[8..15] → Count
Set 0xFFFF (65535) for up-counter mode
80 REG_DIG_IN2_SETUP RW [] BIT BIT[0..7] → Time
BIT[8..15] → Count
Set 0xFFFF (65535) for up-counter mode
81 REG_DIG_IN3_SETUP RW [] BIT BIT[0..7] → Time
BIT[8..15] → Count
Set 0xFFFF (65535) for up-counter mode
82 REG_ADC_IN0_LL RW [mV]
83 REG_ADC_IN0_L RW [mV]
84 REG_ADC_IN0_H RW [mV]
85 REG_ADC_IN0_HH RW [mV]
86 REG_ADC_IN1_LL RW [mV]
87 REG_ADC_IN1_L RW [mV]
88 REG_ADC_IN1_H RW [mV]
89 REG_ADC_IN1_HH RW [mV]
90 REG_ADC_IN2_LL RW [mV]
91 REG_ADC_IN2_L RW [mV]
92 REG_ADC_IN2_H RW [mV]
93 REG_ADC_IN2_HH RW [mV]
94 REG_ADC_IN3_LL RW [mV]
95 REG_ADC_IN3_L RW [mV]
96 REG_ADC_IN3_H RW [mV]
97 REG_ADC_IN3_HH RW [mV]
98 REG_ADC_HYSTERESIS RW [mV]
99 REG_IN0_COUNTER_LO RW* []
100 REG_IN0_COUNTER_HI RO []
101 REG_IN1_COUNTER_LO RW* []
102 REG_IN1_COUNTER_HI RO []
103 REG_IN2_COUNTER_LO RW* []
104 REG_IN2_COUNTER_HI RO []
105 REG_IN3_COUNTER_LO RW* []
106 REG_IN3_COUNTER_HI RO []


192 REG_1W_LAST_ID_0 RO [] 1Wire last ID[1,0] (hi, lo)
193 REG_1W_LAST_ID_1 RO [] 1Wire last ID[3,2] (hi, lo)
194 REG_1W_LAST_ID_2 RO [] 1Wire last ID[5,4] (hi, lo)
195 REG_1W_LAST_ID_3 RO [] 1Wire last ID[7,6] (hi, lo)

(*) Any value written in these registers will reset counter (both LO and HI registers) to 0.

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This page was last modified 08:29, 11 March 2016. Content is available under C-Labs Home.